The present invention relates to built-in self-test (BIST) for integrated circuits, and more particularly to on-chip techniques for testing semiconductor memories embedded in application specific integrated circuits.
Integrated circuit devices such as random access memories (RAMs) typically undergo device verification testing during manufacture. Typically, such verification tests are designed to detect both static and dynamic defects in such a memory array. Such static defects include, for example, open circuit and short circuit defects in the integrated circuit device. Dynamic defects include defects such as weak pull-up or pull-down transistors that create timing sensitive defects in such a memory array.
A specialized integrated circuit device tester is normally employed to perform manufacturing verification tests. For example, such an integrated circuit device tester may be used to perform read/write verification cycle tests on the memory array. Relatively low speed, low cost integrated circuit device testers are usually sufficient for detecting static defects in the memory array. However, extremely expensive integrated testers are needed to detect dynamic defects in very high speed memory arrays. Unfortunately, such expensive high speed integrated circuit testers increase the overall manufacturing costs for such devices. In addition, for integrated circuit devices that provide large memory arrays, the cycle time required to perform such read/write tests increases in proportion to the size of the array.
Attempts to overcome some of the difficulties associated with testing integrated circuit devices have included implementing built-in self-test (BIST) circuitry. Various techniques are described in xe2x80x9cBuilt-In Self-Test Techniquesxe2x80x9d by Edward J. McCluskey, IEEE Design and Test of Computers, Vol. 2, No. 2, pp. 21-28, April 1985, and U. S. Pat. Nos. 5,633,877; 5,301156; 4,195,770; 4,974,226; 5,138,619; 5,173,906; 5,258,986; 5,388,104; and 5,471,482.
The BIST circuitry is used for testing a digital logic, an analog core, a memory, and so on. In the memory test, BIST methods are classified into a deterministic test method and a randomized test method. Considering test time and fault coverage of the test, the deterministic test method adopting a March test algorithm is more useful than the randomized test method. The March test algorithm is able to be adopted to various kinds of memories, such as a complied synchronous/asynchronous,RAM, an enhanced data output DRAM (EDO DRAM), a synchronous DRAM, a flash memory, and an electrically erasable and programmable ROM (EEPROM).
For example, an integrated circuit cache memory array may contain circuitry to perform a March pattern on the memory array. A state machine is typically used to generate the March pattern along with circuitry to sample data output and to generate a signature of the results. The signature is then compared against an expected value to determine whether defects exist in the memory array. Such BIST circuitry usually enables high speed testing while obviating expensive high speed testers.
Unfortunately, past BIST routines have. only been able to apply a preprogrammed test sequence on the memory array. For example, a compiled SRAM has simple read/write control and its control timing, so that the BIST circuitry can be constructed easily. However, a DRAM has various reading/writing control methods and its complex timing, so that the DRAM can not be tested sufficiently in consideration of all timing parameters by using the fixed test sequence.
It is therefore an object of the present invention to provide a programmable BIST system for testing a memory device with optimum test patterns depending upon characteristics of the memory device.
It is therefore another object of the present invention to provide a programmable BIST system for increasing a memory test efficiency and its error detection efficiency.
In order to attain the above objects, according to an aspect of the present invention, there is provided a BIST system for a semiconductor memory comprising a parameter register file having a plurality of externally programmable registers for storing parameters to test the memory; a BIST machine for controlling read/write operations of the memory in response to the parameters stored in the parameter register file, and sensing an occurrence of an error according to the read/write operations; and a multi-input signature register (MISR) for compressing test results from the BIST machine.
As is apparent from the foregoing, according to the BIST system of the invention, read/write patterns for testing the memory can be externally programmed, so that the BIST system can test the memory having various reading/writing control methods and its complex timing, with programmed optimum parameters.
According to the programmable BIST system of the invention, the timing characteristics of the memory device can be tested in a developing step of a memory core. Therefore, a memory test efficiency and its error detection efficiency can be increased.